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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13603-4E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90610A Series
MB90611A/MB90613A
s DESCRIPTION
MB90610A series includes 16-bit microcontrollers optimally usable for high-speed real-time data processing in consumer appliances and for system control of printer, CD-ROM, celluar phone, copier, etc. The series uses the *F2MC-16L CPU which is based on the F2MC-16 but with enhanced high-level language and task switching instructions and additional addressing modes. The internal peripheral resources consist of a 3-channel serial port incorporating a UART function (and supporting I/O expansion serial mode), 8-channel 10-bit A/D converter, 2-channel PPG, 2-channel 16-bit reload timer, 8-channel chip select output, and 8-channel external interrupts. Also, multiplexed or non-multiplexed operation can be selected for the address/data bus. *: "F2MC is an abbreviation for "Fujitsu Flexible Microcontroller".
s FEATURES
* F2MC-16L CPU * Minimum instruction execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4 * Instruction set optimized for controller applications Upward object code compatibility with F2MC-16 (H) Wide range of data types (bit/byte/word/long word) Improved instruction cycles provide increased speed Additional addressing modes: 23 modes High code efficiency Access methods (bank access/linear pointer) Enhanced multiplication and division instructions (signed instructions added) High precision operations are enhanced by use of a 32-bit accumulator Extended intelligent I/O service (access area extended to 64 Kbytes) Maximum memory space: 16 Mbytes
(Continued)
s PACKAGE
100-pin Plastic LQFP 100-pin Plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90610A Series
(Continued) * Enhanced high level language (C)/multitasking support instructions Use of a system stack pointer Enhanced pointer indirect instructions Barrel shift instructions Stack check function * Improved execution speed: Four byte instruction queue * Powerful interrupt function * Automatic data transfer function (does not use instructions)
Internal peripherals * RAM: 1 Kbyte (MB90611A) 3 Kbytes (MB90613A) * General purpose ports 8, 16-bit data bus, multiplexed mode : 57 ports max. 16-bit non-multiplexed mode : 41 ports max. 8-bit non-multiplexed mode : 49 ports max. * UART (SCI): 3 channels For either asynchronous or clocked serial transfer (I/O expansion serial) * A/D converter: 8 channels (10-bit) 8-bit conversion mode also available * PPG (programmable pulse generator): 2 channels * 16-bit reload timer: 2 channels * Chip select output: 8 channels * External interrupts: 8 channels * 18-bit timebase timer Watchdog timer function * PLL clock multiplier function * CPU intermittent operation function * Various standby modes * LQFP-100/QFP-100 package * CMOS technology
2
MB90610A Series
s PRODUCT LINEUP
Part No. Parameter Classification ROM size RAM size CPU functions 1 Kbyte Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time : : : : : : MB90611A Mask ROM -- 3 Kbytes 340 8/16 bits 1 to 7 bytes 1/4/8/16/32 bits 62.5 ns/4 MHz (PLL multiplier = 4) 1000 ns/16 MHz (minimum) MB90613A
Ports
I/O ports (CMOS/TTL) : 33 (31 CMOS/2 TTL) (N-channel open drain): 8 (16-bit non-multiplex mode) Total : 41 FPT-100P-M05 FPT-100P-M06 Three internal UARTs Full-duplex, double-buffered Selectable clock synchronous or asynchronous operation Built-in dedicated baud rate generator 10-bit x 8 channels A/D conversion time : 6.13 s (98 machine cycles/16 MHz machine clock, includes sample and hold time) Triggers : Software, external, or multi-function timer output (RT0) activation can be selected. Activation modes : Single, scan (continuous conversion of multiple channels), continuous (continuous conversion of one channel), and stop (scan mode with synchronized conversion start) 2 x 8-bit PPG outputs (1 channel PPG output in 16-bit mode) 16-bit reload timer operation (selectable toggle output, one-shot output) (Selectable count clock: 0.125 s, 0.5 s, or 2.0 s for a 16 MHz machine cycle) Selectable event count function, 2 internal channels 8 outputs
Packages UART (SCI)
A/D Converter
PPG 16-Bit Reload Timer Chip select
External interrupts 8 inputs External interrupt mode (Interrupts can be generated from four different types of request signal) PLL Function Other Selectable multiplier: 1/2/3/4 (Set a multiplier that does not exceed the assured operation frequency range.) --
3
MB90610A Series
s PIN ASSIGNMENT
(Top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P21/A01 P20/A00 P17/D15/AD15 P16/D14/AD14 P15/D13/AD13 P14/D12/AD12 P13/D11/AD11 P12/D10/AD10 P11/D09/AD09 P10/D08/AD08 D07/AD07 D06/AD06 D05/AD05 D04/AD04 D03/AD03 D02/AD02 D01/AD01 D00/AD00 VCC X1 X0 VSS ALE RD P55/WRL
P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 P30/A08 P31/A09 VSS P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/A20 VCC P45/A21 P46/A22 P47/A23 P70/INT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P94/SOT2 P93/SIN2 P92/SCK1 P91/SOT1 P90/SIN1 P86/SCK0 P85/SOT0 P84/SIN0 P83/TOT1 P82/TOT0
4
P71/INT1 P72/INT2 P73/INT3 P74/INT4/PPG0 P75/INT5/PPG1 P76/INT6/ATG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/INT7/TIN0 P81/TIN1 MD0 MD1 MD2 HST
(FPT-100P-M05)
MB90610A Series
(Top view)
P17/D15/AD15 P16/D14/AD14 P15/D13/AD13 P14/D12/AD12 P13/D11/AD11 P12/D10/AD10 P11/D09/AD09 P10/D08/AD08 D07/AD07 D06/AD06 D05/AD05 D04/AD04 D03/AD03 D02/AD02 D01/AD01 D00/AD00 VCC X1 X0 VSS P20/A00 P21/A01 P22/A02 P23/A03 P24/A04 P25/A05 P26/A06 P27/A07 P30/A08 P31/A09 VSS P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P44/A20 VCC P45/A21 P46/A22 P47/A23 P70/INT0 P71/INT1 P72/INT2 P73/INT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ALE RD P55/WRL RST P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK PA7/CS7 PA6/CS6 PA5/CS5 PA4/CS4 PA3/CS3 PA2/CS2 PA1/CS1 CS0 P95/SCK2 P94/SOT2 P93/SIN2 P92/SCK1 P91/SOT1 P90/SIN1 P86/SCK0 P85/SOT0 P84/SIN0 P83/TOT1 P82/TOT0 HST MD2
P74/INT4/PPG0 P75/INT5/PPG1 P76/INT6/ATG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/INT7/TIN0 P81/TIN1 MD0 MD1
(FPT-100P-M06)
5
MB90610A Series
s PIN DESCRIPTION
Pin no. LQFP*1 80 81 83 to 90 QFP*2 82 83 Pin name X0 X1 Circuit type A Crystal oscillator pins (Oscillator) K (TTL) In non-multiplex mode, the I/O pins for the lower 8 bits of the external data bus. In multiplexed mode, the I/O pins for the lower 8 bits of the external address/data bus. K (TTL) General purpose I/O ports This applies in non-multiplexed mode with an 8-bit external data bus. In non-multiplexed mode, the I/O pins for the upper 8 bits of the external data bus This applies when using a 16-bit external data bus. In multiplexed mode, the I/O pins for the upper 8 bits of the external address/data bus. B (CMOS) General purpose I/O ports This applies in multiplexed mode. In non-multiplexed mode, the output pins for the lower 8 bits of the external address bus. B (CMOS) General purpose I/O ports This applies in multiplexed mode. In non-multiplexed mode, the output pins for the upper 8 bits of the external address bus. B (CMOS) General purpose I/O ports This applies when the upper address control register specifies port operation. The output pins for A16 to 23 of the external address bus This applies when the upper address control register specifies address operation. H General purpose I/O ports (CMOS/H) This applies in all cases. External interrupt request input pins As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. Function
85 to 92 D00 to D07 AD00 to AD07
91 to 98 93 to 100 P10 to P17
P08 to D15
AD08 to AD15 99 100 1 to 6 7 8 10 to 15 16 to 20 22 to 24 1 to 8 P20 to P27 A00 to A07 9 P30 to P37 10 12 to 17 A08 to A15 18 to 22 P40 to P47 24 to 26 A16 to A23
25 to 28
27 to 30 P70 to P73 INT0 to INT3
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
6
MB90610A Series
Pin no. LQFP*1 29 30 QFP*2 31 32
Pin name P74, P75
Circuit type
Function
H General purpose I/O ports (CMOS/H) This applies when the waveform outputs for PPG timers 0 to 1 are disabled. External interrupt request input pins As the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. Output pins for PPG timers 0 to 1 This applies when the waveform outputs for PPG timers 0 to 1 are enabled. H General purpose I/O port (CMOS/H) This applies in all cases. H External interrupt request input pin (CMOS/H) As the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. Trigger input pin for the A/D converter As the input operates continuously when the A/D converter inputs are operating, output to the pin from other functions must be stopped unless done intentionally. Power supply Power supply Power supply Power supply C (AD) Power supply for the analog circuits Do not switch this power supply on/off unless a voltage greater than AVCC is applied to VCC. Analog circuit reference voltage input Do not switch the voltage to this pin on/off unless a voltage greater than AVRH is applied to AVCC. Analog circuit reference voltage input Ground level for the analog circuits Open-drain output ports This applies when port operation is specified in the analog input enable register. Analog input pins for the A/D converter This applies when analog input mode operation is specified in the analog input enable register. H General purpose I/O port (CMOS/H) This applies in all cases. External interrupt request input pin As the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. Event input pin for reload timer 0 As the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally.
INT4, INT5
PPG0, PPG1
31
33
P76 INT6
ATG
32
34
AVCC
33
35
AVRH
34 35 36 to 39 41 to 44
36 37
AVRL AVSS
38 to 41 P60 to P67 43 to 46 AN0 to AN7
45
47
P80 INT7
TIN0
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
7
MB90610A Series
Pin no. LQFP*1 46 QFP*2 48
Pin name P81 TIN1
Circuit type D General purpose I/O port (CMOS/H) This applies in all cases.
Function
Event input pin for reload timer 1 As the input operates continuously when the reload timer is set to input operation, output to the pin from other functions must be stopped unless done intentionally. E Input pins for specifying an oprating mode (CMOS/H) Connect directly to VCC or VSS. M Input pins for specifying an oprating mode (CMOS/H) Connect directly to VCC or VSS. F Hardware standby input pin (CMOS/H) D General purpose I/O ports (CMOS/H) This applies when output is disabled for reload timers 0 to 1. Output pins for reload timers 0 to 1 This applies when output is enabled for reload timers 0 to 1. D General purpose I/O port (CMOS/H) This applies in all cases. Serial data input pin for UART0 As the input operates continuously when UART0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART0. Serial data output pin for UART0 This applies when serial data output is enabled for UART0. D General purpose I/O port (CMOS/H) This applies when the UART0 clock output is disabled. Clock I/O pin for UART0 This applies when the UART0 clock output is enabled. As the input operates continuously when UART0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies in all cases. Serial data input pin for UART1 As the input operates continuously when UART1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally.
47, 48 49 50 51, 52
49, 50 51 52 53, 54
MD0, MD1 MD2 HST P82, P83 TOT0, TOT1
53
55
P84 SIN0
54
56
P85 SOT0
55
57
P86 SCK0
56
58
P90 SIN1
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
8
MB90610A Series
Pin no. LQFP*1 57 QFP*2 59
Pin name P91 SOT1
Circuit type
Function
D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART1. Serial data output pin for UART1 This applies when serial data output is enabled for UART1. D General purpose I/O port (CMOS/H) This applies when the UART1 clock output is disabled. Clock I/O pin for UART1 This applies when the UART1 clock output is enabled. As the input operates continuously when UART1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies in all cases. Serial data input pin for UART2 As the input operates continuously when UART2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. D General purpose I/O port (CMOS/H) This applies when serial data output is disabled for UART2. Serial data output pin for UART2 This applies when serial data output is enabled for UART2. D General purpose I/O port (CMOS/H) This applies when the UART2 clock output is disabled. Clock I/O pin for UART2 This applies when the UART2 clock output is enabled. As the input operates continuously when UART2 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. J (CMOS) I (CMOS) Chip select pin for program ROM General purpose I/O ports This applies for pins with chip select output disabled by the chip select control register. Output pins for the chip select function This applies for pins with chip select output enabled by the chip select control register. I (CMOS) General purpose I/O port This applies when CLK output is enabled. CLK output pin
58
60
P92 SCK1
59
61
P93 SIN2
60
62
P94 SOT2
61
63
P95 SCK2
62 63 to 69
64
CS0
65 to 71 PA1 to PA7
CS1 to CS7
70
72
P50 CLK
*1: FPT-100P-M05 *2: FPT-100P-M06
(Continued)
9
MB90610A Series
(Continued)
Pin no. LQFP*1 71 QFP*2 73 Pin name P51 RDY 72 74 P52 HAK 73 75 P53 HRQ 74 76 P54 I (CMOS) L (TTL) I (CMOS) Circuit type L (TTL) Function General purpose I/O port This applies when the external ready function is disabled. Ready input pin This applies when the external ready function is enabled. General purpose I/O port This applies when the hold function is disabled. Hold acknowledge output pin This applies when the hold function is enabled. General purpose I/O port This applies when the hold function is disabled. Hold request input pin This applies when the hold function is enabled. General purpose I/O port This applies in 8-bit external bus mode or when output is disabled for the WR pin. Write strobe output pin for the upper 8 bits of the data bus This applies in 16-bit external bus mode and when output is enabled for the WR pin. G External reset request input pin (CMOS/H) I (CMOS) General purpose I/O port This applies when output is disabled for the WR pin. Write strobe output pin for the lower 8 bits of the data bus This applies when output is enabled for the WR pin. J (CMOS) J (CMOS) Power supply Power supply Read strobe output pin for the data bus ALE (address latch enabling) output pin Power supply for the digital circuits Ground level for the digital circuits
WRH
75 76
77 78
RST P55 WRL
77 78 21, 82 9, 40, 79
79 80 23, 84 11, 42, 81
RD ALE VCC VSS
*1: FPT-100P-M05 *2: FPT-100P-M06
10
MB90610A Series
s I/O CIRCUIT TYPE
Type A
X1 Clock input X0
Circuit
Remarks * Max. 3 to 32 MHz * Oscillator feedback resistance: approximately 1 M
Standby control
B
Digital output
* CMOS level I/O With standby control
R
Digital output
Digital input Standby control
C
R Digital output
* N-channel open drain output * CMOS level hysteresis input With AD control
A/D input Digital input A/D Disable
D
Digital output
* CMOS level output * CMOS level hysteresis input With standby control
R
Digital output
Digital input Standby control
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the "L" level or when in the standby state. (Continued)
11
MB90610A Series
Type E
Circuit
Remarks * CMOS level input No standby control
R
Digital input
F
* CMOS level hysteresis input No standby control
R
Digital input
G
* CMOS level hysteresis input No standby control * With pull-up
R
Digital input
H
Digital output
* CMOS level output * CMOS level hysteresis input No standby control
R
Digital output
Digital input
I
Standby control
* CMOS level I/O * Pull-up resistor approximately 50 k * Pin goes to high impedance during stop mode.
Digital output
R
Digital output
Digital input Standby control
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the "L" level or when in the standby state. (Continued) 12
MB90610A Series
(Continued)
Type J
Standby control
Circuit
Remarks * CMOS level output * Pull-up resistor approximately 50 k * Pin goes to high impedance during stop mode.
Digital output
Digital output
K
Digital output
* CMOS level output * TTL level input With standby control
R
Digital output
Digital input Standby control
L
Standby control
Digital output
* * * *
CMOS level output TTL level input Pull-up resistor approximately 50 k Pin goes to high impedance during stop mode.
R
Digital output
Digital input Standby control
M
* CMOS level input No standby control
R
Digital input
Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the "L" level or when in the standby state.
13
MB90610A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if the voltage applied between VCC and VSS exceeds the rating. If latchup occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation. For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an "L" level to the RST pin, ensure that the "L" level is applied for at least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Cautions When Using an External Clock
Drive the X0 pin only when using an external clock. * Using an External Clock
MB90610A Series X0
OPEN
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always cut the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before disconnecting the digital power supply (VCC). When turning the power on or off, ensure that AVRH does not exceed AVCC. Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
14
MB90610A Series
s BLOCK DIAGRAM
X0, 1 RST HST MD0 to MD2
7
Clock control circuit
CPU F2MC-16L family core Interrupt controller
RAM
Communication prescaler 3 SIN0 to SIN2 SOT0 to SOT2 SCK0 to SCK2 AVcc AVRH, AVRL AVss ATG AN0 to AN7 A00 to A23 D00 to D15 ALE RD WRL, WRH HRQ HAK RDY CLK 3 3 UART F2MC-16 bus
8/16-bit PPG (output switching) x 1channel
PPG0 PPG1
2 A/D converter (8/10-bit) 8 24 16
8 External interrupts 2 2 External bus Interface Reload timer 2 8 Chip select outputs CS0 to CS7 IRT0 to IRT7
TIT0, TIT1 TOT0, TOT1
I/O ports 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 6 P50 to P55 8 P60 to P67 7 P70 to P76 7 P80 to P86 6 P90 to P95 7 PA1 to PA7
15
MB90610A Series
s F2MC-16L CPU PROGRAMMING MODEL
* Dedicated Registers
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General-purpose Registers
32 banks (max.)
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4 RL1
RW2 RW1 RL0 000180H + RP x 10H RW0 16 bits
* Processor States (PS)
ILM RP I S T N CCR Z V C
16
MB90610A Series
s MEMORY MAP
FFFFFFH External ROM/External bus
002000H Address 3# 000380H RAM 000180H 000100H 0000C0H Peripherals 000000H : Internal : External : No access Registers
Type MB90611A MB90613A
Address #3 000500H 000D00H
17
MB90610A Series
s I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH to 10H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH to 1FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H Free Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Vacancy Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Analog input enable register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Vacancy Serial mode register 0 Serial control register 0 Serial input data register 0/ Serial output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Serial input data register 1/ Serial output data register 1 Serial status register 1 Register Name -- PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA -- DDR1 DDR2 DDR3 DDR4 DDR5 ADER DDR7 DDR8 DDR9 DDRA -- SMR0 SCR0 SIDR0/ SODR0 SSR0 SMR1 SCR1 SIDR1/ SODR1 SSR1 Access *3 R/W* R/W* R/W* R/W R/W R/W R/W R/W R/W R/W *3 R/W* R/W* R/W* R/W R/W R/W R/W R/W R/W R/W *3 R/W! R/W! R/W R/W! R/W! R/W! R/W R/W! UART1 (SCI) UART0 (SCI) Port 1*8 Port 2
*7
Resource name -- Port 1
*8
Initial value -- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX - - XXXXXX 11111111 - XXXXXXX - XXXXXXX - - XXXXXX XXXXXXX -
Port 2*7 Port 3*7 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A --
-- 00000000 00000000 00000000 00000000 --000000 11111111 -0000000 -0000000 --000000 0000000-
Port 3*7 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A --
-- 00000000 00000100 XXXXXXXX 00001-00 00000000 00000100 XXXXXXXX 00001-00
(Continued)
18
MB90610A Series
Address 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H
Register Interrupt/DTP enable register Interrupt/DTP request register Interrupt level setting register AD control status register AD data register PPG0 operation mode control register PPG1 operation mode control register
Name ENIR EIRR ELVR ADCS ADCR PPGC0 PPGC1 -- PRL0 PRL1 TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 -- SMR2 SCR2 SIDR2/ SODR2 SSR2 CSCR0 CSCR1 CSCR2 CSCR3
Access R/W R/W R/W R/W!
Resource name
Initial value 00000000 00000000 00000000 00000000 00000000 00000000 XXXXXXXX 0 0 0 0 0 0XX
DTP/external interrupt
A/D converter R/W! *4 R/W R/W *3 R/W R/W R/W! 16-bit reload timer 0 R/W R/W! 16-bit reload timer 1 R/W *3 R/W! R/W! R/W R/W! R/W R/W R/W R/W Chip select function UART2 (SCI) -- PPG0 PPG1 PPG0 PPG1 --
000000-1 000000-1 -- XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 ----0000 XXXXXXXX XXXXXXXX 00000000 ----0000 XXXXXXXX XXXXXXXX -- 00000000 00000100 XXXXXXXX 00001-00 ----0000 ----0000 ----0000 ----0000
000032H, Vacancy 33H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H to 43H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH PPG0 reload register PPG1 reload register Control status register 16-bit timer register/ 16-bit reload register Control status register 16-bit timer register/ 16-bit reload register Vacancy Serial mode register 2 Serial control register 2 Serial input data register 2/ Serial output data register 2 Serial status register 2 CS control register 0 CS control register 1 CS control register 2 CS control register 3
(Continued)
19
MB90610A Series
Address 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H to 8FH 000090H to 9EH 00009FH 0000A0H 0000A1H 0000A2H to A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH to AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H
Register CS control register 4 CS control register 5 CS control register 6 CS control register 7 Vacancy
Name CSCR4 CSCR5 CSCR6 CSCR7 --
Access*2 R/W R/W R/W R/W *3 W *3 W *3 W *3 *1 R/W R/W! R/W! *3 W W W R/W! R/W! *3 R/W! R/W! R/W! R/W! R/W! R/W!
Resource name Chip select function -- UART0 (SCI) -- UART1 (SCI) -- UART2 (SCI) -- -- Delayed interrupt generation module Low power consumption Low power consumption -- External pins External pins External pins Watchdog timer Timebase timer --
Initial value ----0000 ----0000 ----0000 ----0000 -- ----1111 -- ----1111 -- ----1111 -- -- -------0 00011000 11111100 -- 0011--00 00000000 -000*000 XXXXX 1 1 1 1--00100 -- 00000111 00000111
UART0 (SCI) machine clock division CDCR0 control register Vacancy -- UART1 (SCI) machine clock division CDCR1 control register Vacancy -- UART2 (SCI) machine clock division CDCR2 control register Vacancy Reserved system area Delayed interrupt generate/ release register Low power consumption mode control register Clock selection register Vacancy Auto-ready function selection register External address output control register Bus control signal selection register Watchdog timer control register Timebase timer control register Vacancy Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 -- -- DIRR LPMCR CKSCR -- ARSR HACR ECSR WDTC TBTC -- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05
Interrupt controller
00000111 00000111 00000111 00000111
(Continued)
20
MB90610A Series
(Continued) Address
0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to FFH
Register Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 External area *2
Name ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 --
Access R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! --
Resource name
Initial value 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
Interrupt controller
--
--
Initial values 0 : The initial value for this bit is "0". 1 : The initial value for this bit is "1". * : The initial value for this bit is "1" or "0". (Determined by the level of the MD0 to MD2 pins.) X : The initial value for this bit is undefined. - : This bit is not used. The initial value is undefined. *1: Access prohibited. *2: This is the only external access area in the area below address 0000FFH. Access this address as an external I/O area. *3: Areas marked as "free" in the I/O map are reserved areas. These areas are accessed by internal access. No access signals are output on the external bus. *4: Only bit 15 can be written. The other bits are written to by the test function. Reading bits 10 to 15 returns zeros. *5: The R/W! symbol in the Read/Write column indicates that some bits are read-only or write-only. See the resource's register list for details. *6: Using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated by R/W!, R/W*, or W in the Read/Write column sets the specified bit to the desired value. However, this can cause misoperation if the other register bits include write-only bits. Therefore, do not use read-modify-write instructions to access these registers. *7: This register is only available when the address/data bus is in multiplex mode. Access to the register is prohibited in non-multiplex mode. *8: This register is only available when the external data bus is in 8-bit mode. Access to the register is prohibited in 16-bit mode. Note: The initial values listed for write-only bits are the initial values set by a reset. They are not the values returned by a read. Also, LPMCR/CKSCR/WDTC are sometimes initialized and sometimes not initialized, depending on the reset type. The listed initial values are for when these registers are initialized.
21
MB90610A Series
s INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO INTERRUPT SOURCES
Interrupt source Reset INT 9 instruction Exception External interrupt #0 External interrupt #1 External interrupt #2 External interrupt #3 External interrupt #4 External interrupt #5 External interrupt #6 UART0 * transmit complete External interrupt #7 UART1 * transmit complete PPG #0 PPG #1 16-bit reload timer #0 16-bit reload timer #1 A/DC measurement complete UART2 * transmit complete Timebase timer interval interrupt UART2 * receive complete UART1 * receive complete UART0 * receive complete Delayed interrupt generation module x x x x I2OS support x x x Interrupt vector Number #08 #09 #10 #11 #13 #15 #17 #19 #21 #23 #24 #25 #26 #27 #28 #29 #30 #31 #33 #34 #35 #37 #39 #42 08H 09H 0AH 0BH 0DH 0FH 11H 13H 15H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 21H 22H 23H 25H 27H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC0H FFFFB8H FFFFB0H FFFFA8H FFFFA0H ICR06 FFFF9CH FFFF98H ICR07 FFFF94H FFFF90H FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H FFFF78H FFFF74H FFFF70H FFFF68H FFFF60H FFFF54H ICR12 ICR13 ICR14 ICR15 0000BCH 0000BDH 0000BEH 0000BFH ICR10 ICR11 0000BAH 0000BBH 0000B9H ICR08 0000B8H 0000B7H 0000B6H Interrupt control register ICR Address
-- -- --
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05
-- -- --
0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request). x : indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS.
22
MB90610A Series
s PERIPHERAL RESOURCES
1. Parallel Port
The MB90610A series has 58 I/O pins, 18 output pins, and 8 open drain output pins. Ports 1 to 5 and ports 7 to A are I/O ports. The ports are inputs when the corresponding direction register bit is "0" and outputs when the corresponding bit is "1". Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2 and 3 are only available when the address/data bus is in multiplex mode. Access is prohibited in nonmultiplex mode. Port 6 is an open drain port. Port 6 pins can only be used as ports when the analog input enable register is "0". (1) Register Configuration
Port data register bit 15 14 13 12 11 10 9 8 Address : PDR1 000001H : PDR3 000003H : PDR5 000005H PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0 : PDR7 000007H : PDR9 000009H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value Port data register 7 6 5 4 3 2 1 0 bit Address : PDR2 000002H : PDR4 000004H : PDR6 000006H PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0 : PDR8 000008H : PDRA 00000AH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value
Notes: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A.
PDRx
PDRx
Port direction register bit Address : DDR1 000011H : DDR3 000013H : DDR5 000015H : DDR7 000017H : DDR9 000019H Read/write Initial value Port direction register bit Address : DDR2 000012H : DDR4 000014H : DDR8 000018H : DDRA 00001AH Read/write Initial value
15
14
13
12
11
10
9
8
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0
DDRx
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
DDRx
23
MB90610A Series
Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A. Port 6 does not have a DDR.
Analog input enable register ADER 000016H Read/write Initial value
(2) Register Details * Port Data Registers
bit
15
14
13
12
11
10
9
8 ADER
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1)
Port data register bit 15 14 13 12 11 10 9 8 Address : PDR1 000001H : PDR3 000003H : PDR5 000005H PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0 : PDR7 000007H : PDR9 000009H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write (X) (X) (X) (X) (X) (X) (X) (X) Initial value Port data register Address : PDR2 000002H : PDR4 000004H : PDR6 000006H : PDR8 000008H : PDRA 00000AH Read/write Initial value bit 7 6 5 4 3 2 1 0
PDRx
PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
PDRx
Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bits are provided for bits 6 to 7 of port 9. No register bit is provided for bit 0 of port A. Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2, 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode.
24
MB90610A Series
* Port Direction Registers
Port direction register bit Address : DDR1 000011H : DDR3 000013H : DDR5 000015H : DDR7 000017H : DDR9 000019H Read/write Initial value Port direction register bit Address : DDR2 000012H : DDR4 000014H : DDR8 000018H : DDRA 00001AH Read/write Initial value
15
14
13
12
11
10
9
8
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0
DDRx
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
DDRx
When pins are used as ports, the register bits control the corresponding pins as follows. 0: Input mode 1: Output mode Bits are set to "0" by a reset. Note: No register bits are provided for bit 6 to 7 of port 5. No register bit is provided for bit 7 of port 7. No register bit is provided for bit 7 of port 8. No register bit is provided for bit 0 of port A. No register bits are provided for bits 6 to 7 of port 9. Port 6 does not have a DDR. Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode. Ports 2 and 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode. * Analog Input Enable Register
bit Analog input enable register ADER 000016H Read/write Initial value
15
14
13
12
11
10
9
8 ADER
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1)
Controls each pin of port 6 as follows. 0: Port input mode 1: Analog input mode Bits are set to "1" by a reset. Note: Inputting an intermediate level signal in port input mode causes an input leak current to flow. Therefore, set to analog input mode when applying an analog input.
25
MB90610A Series
(3) Block Diagrams * I/O Port
Internal data bus
Data register read Data register Data register write Direction register Direction register write Pin
Direction register read
* Open Drain Port (Also used as Analog Inputs)
Internal data bus RMW (Read-modify-write instruction)
Data register read Data register Data register write ADER ADER register write
Pin
ADER register read
26
MB90610A Series
(4) Port Pin Allocation Ports 1, 2, 3, 4, and 5 on the MB90610A series share pins with the external bus. The pin functions are determined by the bus mode and register settings. Function Non-multiplex mode Pin External address control Enable (address) External bus width 8-bit D07 to D00 AD07 to AD00 P17 to P10/ D15 to D08/ AD15 to AD08 P27 to P20/ A07 to A00 P37 to P30/ A15 to A08 P47 to P40/ A23 to A16 P57/ALE RD P55/WRL P54/WRH P53/HRQ P52/HAK P51/RDY P50/CLK Port WRH HRQ HAK RDY CLK 16-bit Disable (port) External bus width 8-bit 16-bit Multiplex mode External address control Enable (address) External bus width 8-bit 16-bit Disable (port) External bus width 8-bit 16-bit
D07 to D00
AD07 to AD00
Port
D15 to D08
Port
D15 to D08
A15 to A08
AD15 to AD08
A15 to A08
AD15 to AD08
A07 to A00 A15 to A08 A23 to A16 ALE RD WRL
A07 to A00 Port A15 to A08 Port A23 to A16 ALE RD WRL Port WRH Port WRH HRQ HAK RDY CLK Port WRH Port
Note: The upper address, WRL, WRH, HAK, HRQ, RDY, and CLK can be set for use as ports by function selection.
27
MB90610A Series
2. UART 0/1/2 (SCI)
UART 0/1/2 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK synchronous (I/O expansion serial) data transfer. The ports have the following features. * Full duplex, double buffered * Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data transfer * Multi-processor mode support * Built-in dedicated baud rate generator CLK asynchronous: 62500/31250/19230/9615/4808/2404/1202 bps CLK synchronous: 2 M/1 M/500 K/250 K bps * Supports flexible baud rate setting using an external clock * Error detect function (parity, framing, and overrun) * NRZ type transmission signal * Intelligent I/O service support (1) Register Configuration
Serial mode register Address : channel 0 000020H : channel 1 000024H : channel 2 000044H Read/write Initial value Serial control register Address : channel 0 000021H : channel 1 000025H : channel 2 000045H Read/write Initial value Input data register/ Output data register Address : channel 0 000022H : channel 1 000026H : channel 2 000046H Read/write Initial value Serial status register Address : channel 0 000023H : channel 1 000027H : channel 2 000047H Read/write Initial value Machine clock division control register Address : channel 0 000051H : channel 1 000053H : channel 2 000055H Read/write Initial value
28
bit
7 MD1
6 MD0
5 CS2 (W) (0) 13 SBL CL
4 CS1 (W) (0) 12
3 CS0 (W) (0) 11 A/D - (-) (-)
2
1
0 SMR
SCKE SOE (R/W) (R/W) (0) (0) 10 9 RXE 8 TXE
(R/W) (R/W) (0) (0) bit 15 PEN P 14
REC
SCR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0) bit 7 6 5 4 3 2 1 0
D7
D6
D5
D4
D3
D2
D1
D0
SIDR (read) SODR (write)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit PE (R) (0) bit 15 15 14 ORE (R) (0) 14 13 12 11 - (-) (-) 11 10 10 RIE 9 TIE 8 SSR
FRE RDRF TDRE (R) (0) 13 (R) (0) 12 (R) (1)
(R/W) (R/W) (0) (0) 9 8
- (-) (-)
- (-) (-)
- (-) (-)
- (-) (-)
DIV3 DIV1 DIV1 DIV0 (W) (1) (W) (1) (W) (1) (W) (1)
CDCR
MB90610A Series
(2) Block Diagram
Control signals Receive interrupt (to CPU) Dedicated baud rate generator 16-bit timer 0 (Internal connection) Transmit clock Clock select circuit Receive clock
SCK Transmit interrupt (to CPU)
External clock Receive control circuit Transmit control circuit
SIN
Start bit detect circuit Receive bit counter
Transmit start circuit
Transmit bit counter
Receive parity counter
Transmit parity counter
SOT
Receive status evaluation circuit
Receive shifter
Transmit shifter
Receive error indication signal for EI2OS (to CPU)
Receive complete SIDR
Transmit start SODR
F2MC-16 bus
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signals
29
MB90610A Series
3. 10-bit 8-input A/D Converter (With 8-bit Resolution Mode)
The 10-bit 8-input A/D converter converts analog input voltages to digital values. The A/D converter has the following features. * Conversion time: Minimum of 6.13 s per channel (98 machine cycles/16 MHz machine clock. This includes the sample and hold time) * Sample and hold time: Minimum of 3.75 s per channel (60 machine cycles/16 MHz machine clock) * Uses RC-type successive approximation conversion with a sample and hold circuit. * 10-bit or 8-bit resolution * Eight program-selectable analog input channels Single conversion mode : Selectively convert a one channel. Scan conversion mode : Continuously convert multiple channels. Maximum of 8 program-selectable channels. : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.)
Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode
* An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. * Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register Configuration
bit 15 14 A/D control status register (upper) BUSY INT Address : 00002DH Read/write Initial value bit A/D control status register (lower) Address : 00002CH Read/write Initial value A/D data register (upper) Address : 00002EH Read/write Initial value A/D data register (lower) Address : 00002FH Read/write Initial value bit bit
13
12
11
10
9
8
Reserved
INTE PAUS STS1 STS0 STRT (W) (0) 1
ADCS1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) 7 MD1 6 5 4 3 2
(-) (0) 0 ADCS0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 S10 (R/W) (0) 7 D7 (R) (X) 14 - (R) (0) 6 D6 (R) (X) 13 - (R) (0) 5 D5 (R) (X) 12 - (R) (0) 4 D4 (R) (X) 11 - (R) (0) 3 D3 (R) (X) 10 - (R) (0) 2 D2 (R) (X) 9 D9 (R) (X) 1 D1 (R) (X) 8 D8 (R) (X) 0 D0 (R) (X) ADCR0 ADCR1
30
MB90610A Series
(2) Block Diagram
AVCC
AVRH AVRL
AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Successive approximation register
Comparator
Sample and hold circuit Data bus ADCS ATG Trigger activation Timer activation Operating clock
Decoder
Data register ADCR
A/D control register 1 A/D control register 2
Timer (Reload timer 1 output)
Prescaler
31
MB90610A Series
4. 8/16-bit PPG
This block contains the 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. * 8-bit PPG output in 2-channel independent operation mode: Two independent PPG output channels are available. * 16-bit PPG output operation mode : One 16-bit PPG output channel is available. * 8+8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. * PPG output operation: Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register Configuration
bit PPG0 operation mode control register Address : channel 0 000030H Read/write Initial value bit PPG1 operation mode control register Address : channel 1 000031H Read/write Initial value bit Reload register H Address : channel 0 000035H : channel 1 000037H Read/write Initial value bit Reload register L Address : channel 0 000034H : channel 1 000036H Read/write Initial value
7 PEN0
6 --
5
4
3
2
1
0
Reserved
POE0 PIE0 PUF0 PCM1 PCM0
PPGC0
(R/W) (--) (R/W) (R/W) (R/W) (R/W) (R/W) (--) (0) (0) (0) (0) (0) (0) (0) (1) 15 14 13 12 11 10 9 MD0 8
Reserved
PEN1 PCS1 POE1 PIE1 PUF1 MD1
PPGC1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (--) (0) (0) (0) (0) (0) (0) (0) (1) 15 14 13 12 11 10 9 8 PRLH0, 1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 PRLL0, 1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
32
MB90610A Series
(2) Block Diagram * 8/16-bit PPG (channel 0)
Output enable
PPG0
Peripheral clock divided by 16 Peripheral clock divided by 4 Peripheral clock PPG0 output latch Invert Clear PEN0
Count clock selection Timebase counter output Main clock divided by 512
PCNT (down-counter) Reload
S RQ
IRQ
ch.1 borrow L/H select L/H selector
PRLL0
PRLBH0 PIE 0
PRLH0
PUF0 L-side data bus H-side data bus
PPGC0 (Operation mode control)
33
MB90610A Series
* 8/16-bit PPG (channel 1)
Output enable
PPG1
Peripheral clock PPG1 output latch Invert Count clock selection channel 0 borrow Timebase counter output Main clock divided by 512 PCNT (down-counter) Reload L/H selector S RQ Clear
PEN1
IRQ
L/H select
PRLL1
PRLBH1 PIE1
PRLH1
PUF1 L-side data bus H-side data bus
PPGC1 (Operation mode control)
34
MB90610A Series
5. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, one input (TIN) and one output (TOT) pin, and a control register. The input clock can be selected from one external clock and three types of internal clock. The output pin (TOT) outputs a toggle waveform in reload mode and a rectangular waveform during counting in one-shot mode. The input pin (TIN) functions as the event input in event count mode and as the trigger input or gate input in internal clock mode. This product has two internal 16-bit reload timer channels. (1) Register Configuration
Timer control status register (upper) Address : channel 0 000039H : channel 1 00003DH Read/write Initial value Timer control status register (lower) Address : channel 0 000038H : channel 1 00003CH Read/write Initial value 16-bit timer register (upper)/ 16-bit reload register (upper) Address : channel 0 00003BH : channel 1 00003FH Read/write Initial value 16-bit timer register (lower)/ 16-bit reload register (lower) Address : channel 0 00003AH : channel 1 00003EH Read/write Initial value
bit --
15 --
14 --
13 --
12
11
10
9
8
CSL1 CSL2 MOD2 MOD1
(--) (--) bit 7
(--) (--) 6
(--) (--) 5
(--) (R/W) (R/W) (R/W) (R/W) (--) (0) (0) (0) (0) 4 3 UF 2 1 0 TMCSR
MOD0 OUTE OUTL RELD INTE
CNTE TRG
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 14 13 12 11 10 9 8
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 7 6 5 4 3 2 1 0 TMR/ TMRLR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X)
35
MB90610A Series
(2) Block Diagram
16 16-bit reload register
8
Reload RELD 16-bit down-counter UF OUTE OUTL GATE CSL1 Clock selector CSL0 TRG CNTE Clear I2OSCLR Port (TIN) Output enable 3 Prescaler Clear MOD2 MOD1 Peripheral clock MOD0 Serial baud rate A/DC Port (TOUT) OUT CTL INTE UF IRQ
16 F2MC-16 bus 2
2 IN CTL EXCK ------ 21 23 25
Re-trigger
3
36
MB90610A Series
6. Chip Select Function
This module generates chip select signals to simplify connection of memory or I/O devices. The module has 8 chip select output pins. The hardware outputs the chip select signals from the pins when it detects access of an address in the areas specified in the pin registers. (1) Register Configuration
Address : : : : Address : : : :
000049H 00004BH 00004DH 00004FH 000048H 00004AH 00004CH 00004EH
bit
15 --
14 --
13 --
12 --
11
10
9
8
Chip select control register (odd numbers: CSCR1/3/5/7)
ACTL OPEL CSA1 CSA0
bit
7 --
6 --
5 --
4 --
3
2
1
0
Chip select control register (even numbers: CSCR0/2/4/6)
ACTL OPEL CSA1 CSA0
(2) Block Diagram
Address (from CPU) A23 A16 A15 A08 A07 A00
Address decoder Decode signal Program area Decode
Address decoder
CS0 (For the program ROM area) Chip select control register 0 Chip select control register 1
Selection setting Selection setting
Selector Selector CS1
Chip select control register 6 Chip select control register 7
Selection setting Selection setting
Selector Selector
CS6 CS7
37
MB90610A Series
7. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two request levels ("H" and "L") are provided for extended intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on "H", "L" levels can be selected, giving a total of four types. (1) Register Configuration
bit Interrupt/DTP enable register Address : 000028H Read/write Initial value Interrupt/DTP register Address : 000029H Read/write Initial value Request level setting register (upper) Address : 00002BH Read/write Initial value Request level setting register (lower) Address : 00002AH Read/write Initial value
(2) Block Diagram
7 EN7
6 EN6
5 EN5
4 EN4
3 EN3
2 EN2
1 EN1
0 EN0 ENIR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 ER7 14 ER6 13 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0 EIRR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 LB7 14 LA7 13 LB6 12 LA6 11 LB5 10 LA5 9 LB4 8 LA4
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 7 LB3 6 LA3 5 LB2 4 LA2 3 LB1 2 LA1 1 LB0 0 LA0 ELVR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
F2MC-16 bus 8
Interrupt/DTP enable register 8
Interrupt input
8
Gate
Request F/F
Edge detect circuit
Request input
8
Interrupt/DTP register
8
Request level setting register
38
MB90610A Series
8. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16L CPU can be generated and cleared by software using this module. (1) Register Configuration
Delayed interrupt generate/ bit clear decoder Address : 00009FH Read/write Initial value
(2) Block Diagram
15 -- (--) (--)
14 -- (--) (--)
13 -- (--) (--)
12 -- (--) (--)
11 -- (--) (--)
10 -- (--) (--)
9 --
8 R0 DIRR
(--) (R/W) (--) (0)
F2MC-16 bus
Delayed interrupt generate/clear decoder
Interrupt latch
39
MB90610A Series
9. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller. The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. In addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase timer uses the main clock, regardless of the value of the MCS bit in the CKSCR register. (1) Register Configuration
bit Watchdog timer control register Address : 0000A8H Read/write Initial value
7
6
5
4
3
2
1
0 WT0 (W) (1) 8 TBTC WDTC
PONR STBR WRST ERST SRST WTE WT1 (R) (X) bit 15 (R) (X) 14 -- (--) (--) (R) (X) 13 -- (R) (X) 12 (R) (X) 11 (W) (1) 10 (W) (1) 9
Timebase timer control register Address : 0000A9H Read/write Initial value
(2) Block Diagram
Reserved
TBIE TBOF TBR TBC1 TBC0 (W) (1) (R/W) (R/W) (0) (0)
(--) (1)
(--) (R/W) (R/W) (--) (0) (0)
TBTC TBC1 Selector TBC0 TBR TBIE AND TBOF F2MC-16 bus Q S R
Main clock (OSC oscillator) Clock input 212 214 Timebase timer 216 219 212 214 216 219 TBTRES
Timebase interrupt WDTC WT1 Selector WT0 WTE 2-bit counter OF CLR Watchdog reset activation circuit CLR WDGRST To internal reset activation circuit
PONR STBR WRST ERST SRST
From power-on detection From hardware standby control circuit
RST pin From the RST bit of the STBYC register
40
MB90610A Series
10. Low Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are classified as low power consumption modes. In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock). The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. In PLL sleep mode and main sleep mode, the CPU's operating clock only is stopped and other elements continue to operate. In timer mode, only the timebase timer operates. Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum power consumption. The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal memory, internal resource, or external bus access is performed. This function reduces power consumption by lowering the CPU execution speed while still providing a high-speed clock to internal resources. The PLL clock multiplier ratio can be set to 1, 2, 3, 4 by the CS1, 0 bits. The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) Register Configuration
bit Low power consumption mode control register Address : 0000A0H Read/write Initial value bit Clock select register Address : 0000A1H Read/write Initial value
7 STP (W) (0) 15
Reserved
6 SLP (W) (0) 14
5 SPL (R/W) (0) 13
4 RST (W) (1) 12
3
Reserved
2 CG1
1 CG0
0
Reserved
LPMCR
(--) (R/W) (R/W) (--) (1) (0) (0) (0) 11
Reserved
10 MCS
9 CS1
8 CS0 CKSCR
MCM WS1 WS0 (R) (1)
(--) (1)
(R/W) (R/W) (--) (R/W) (R/W) (R/W) (1) (1) (1) (1) (0) (0)
41
MB90610A Series
(2) Block Diagram
CKSCR MCM MCS CKSCR CS1 CS0 LPMCR F2MC-16 bus CG1 CG0 LPMCR SLP STP Standby control circuit
RST Release HST activate
PLL multiplier circuit 1234
Main clock (OSC oscillator) 1/2 CPU clock CPU clock generator 0/9/17/33 Intermittent cycle selection
CPU clock selector
Cycle selection circuit for the CPU intermittent operation function Peripheral clock generator Peripheral clock
HST pin Interrupt request or RST Oscillation stabilization delay time selector 24 213 215 218 Clock input Timebase timer 2
12
CKSCR WS1 WS0 LPMCR SPL
Timebase clock
16
2
14
2
2
19
Pin high impedance control circuit
Pin Hi-Z
LPMCR RST
Internal reset generation circuit
RST pin Internal RST To watchdog timer WDGRST
42
MB90610A Series
* State Transition Diagram for Clock Selection
Power-on
Main MCS = 1 MCM = 1 CS1/0 = XX
(1)
Main PLLX MCS = 0 MCM = 1 (6) CS1/0 = XX
(7)
(2) (3)
(7)
PLL1 Main MCS = 1 MCM = 0 CS1/0 = 00
PLL multiplier = 1 MCS = 0 MCM = 0 (4) (6) CS1/0 = 00
PLL2 Main MCS = 1 MCM = 0 (7) CS1/0 = 01
PLL multiplier = 2 MCS = 0 (6) MCM = 0 CS1/0 = 01
PLL3 Main (7) MCS = 1 MCM = 0 CS1/0 = 10
PLL multiplier = 3
(5) MCS = 0 (6)
MCM = 0 CS1/0 = 10
PLL4 Main MCS = 1 MCM = 0 CS1/0 = 11
(6)
PLL multiplier = 4 MCS = 0 MCM = 0 CS1/0 = 11
(1) (2) (3) (4) (5) (6) (7)
MCS bit cleared PLL clock oscillation stabilization delay complete and CS1/0 = "00" PLL clock oscillation stabilization delay complete and CS1/0 = "01" PLL clock oscillation stabilization delay complete and CS1/0 = "10" PLL clock oscillation stabilization delay complete and CS1/0 = "11" MCS bit set (including a hardware standby or watchdog reset) PLL clock and main clock synchronized timing
43
MB90610A Series
11. Interrupt Controller
The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for each I/O with an interrupt function. The registers have the following three functions. * Set the interrupt level of the corresponding peripheral. * Select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the extended intelligent I/O service. * Select the extended intelligent I/O service channel. (1) Register Configuration
Interrupt control register Address : ICR01 0000B1H : ICR03 0000B3H : ICR05 0000B5H : ICR07 0000B7H : ICR09 0000B9H : ICR11 0000BBH : ICR13 0000BDH : ICR15 0000BFH Read/write Initial value Interrupt control register Address : ICR00 0000B0H : ICR02 0000B2H : ICR04 0000B4H : ICR06 0000B6H : ICR08 0000B8H : ICR10 0000BAH : ICR12 0000BCH : ICR14 0000BEH Read/write Initial value
bit
15
14
13
12
11
10
9
8
ICS3 ICS2
ICS1 ICS0 or or S1 S0
ISE
IL2
IL1
IL0
ICRxx
(W) (0) bit 7
(W) (0) 6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (1) (1) (1) 5 4 3 2 1 0
ICS3 ICS2
ICS1 ICS0 or or S0 S1
ISE
IL2
IL1
IL0
ICRxx
(W) (0)
(W) (0)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (1) (1) (1)
Note: Do not access these registers using read-modify-write instructions as this can cause misoperation.
44
MB90610A Series
(2) Block Diagram
4 I SE I L2 I L1 IL0
4 Determine priority of interrupt or I2OS
32 Interrupt/ I2OS request (peripheral resource)
3 I2OS selection 4 4 I CS3 I CS2 I CS1 I C S 0 4 I2OS vector selection 4 (CPU) Interrupt level I2OS vector (CPU)
F2MC-16 bus
2 S1 S0
2
Detect I2OS completion condition
2 I2OS completion condition
45
MB90610A Series
12. External Bus Terminal Control Circuit
This circuit controls the external bus terminals intended to extend outwardly the CPU's address/data bus. (1) Register Configuration
bit Register for selection of AUTO ready function Address : 0000A5H Read/write Initial value bit Register for control of external address output Address : 0000A6H Read/write Initial value bit Register for selection of bus control signal Address : 0000A7H Read/write Initial value
(2) Block Diagram
15
14
13
12
11 -- (--) (--) 3 E19 (W) (0) 11
10 -- (--) (--) 2 E18 (W) (0) 10
9
8 ARSR
IOR1 IOR0 HMR1 HMR0 (W) (0) 7 E23 (W) (0) 15 -- (--) (--) (W) (0) 6 E22 (W) (0) 14 (W) (1) 5 E21 (W) (0) 13 (W) (1) 4 E20 (W) (0) 12
LMR1 LMR0 (W) (0) 1 E17 (W) (0) 9 RYE (W) (0) (W) (0) 0 E16 (W) (0) 8 CKE (W) (0)
HACR
LMBS WRE HMBS IOBS HDE (W) (0) (W) (0) (W) (1/0) (W) (0) (W) (0)
ECSR
P5 P4 P3 P2 P1 P1 data P1 P5
P1 direction
RB
Data control
Access control Access control
Access control
46
MB90610A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Symbol VCC Power supply voltage AVCC*
1
(VSS = AVSS = 0.0 V)
Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 15 4 100 50 -15 -4 -100 -50 +400 +85 +150
Unit V V V V V mA mA mA mA mA mA mA mA mW C C
Remarks
AVRH*1 AVRL*1 Input voltage*2 Output voltage*2 "L" level maximum output current* "L" level average output current*4 "L" level total maximum output current "L" level total average output current* "H" level maximum output current*3 "H" level average output current*4 "H" level total maximum output current "H" level total average output current*5 Power consumption Operating temperature Storage temperature
5 3
VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Pd TA Tstg
-- -- -- -- -- -- -- -- --
-40 -55
*1: AVCC, AVRH, and AVRL must not exceed VCC. Similarly, it may not exceed AVRL, nor AVRH. *2: VI and VO must not exceed VCC + 0.3 V. *3: The maximum output current must not be exceeded at any individual pin. *4: The average output current is the rating for the current from an individual pin averaged over a duration of 100 ms. *5: The average total output current is the rating for the current from all pins averaged over a duration of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
47
MB90610A Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter Power supply voltage Operating temperature
Symbol VCC TA
Rating Min. 2.7 2.0 -40 Max. 5.5 5.5 +85
Unit V V C
Remarks For normal operation To maintain statuses in stop mode
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
48
MB90610A Series
3. DC Characteristics
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Conditions
"H" level input voltage
VIH VIHS VIHM VIHT VIL VILS VILM VILT --
-- VCC = +5.0 V10% VCC = +3.0 V10% -- VCC = +5.0 V10% VCC = +3.0 V10% VCC = +5.0 V10% Other than P60 IOH = -4.0 mA to P67 VCC = +3.0 V10% IOH = -1.6 mA VCC = +5.0 V10% IOL = -4.0 mA All output pins VCC = +3.0 V10% IOL = -2.0 mA RST, P50 to P55, RD, ALE, PA1 to PA7, CS0
"L" level input voltage
Min. 0.7 VCC 0.8 VCC VCC - 0.3 2.2 0.7 VCC VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5 VCC - 0.3 -- --
Value Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. VCC + 0.3 VCC + 0.3 VCC + 0.3 -- -- 0.3 VCC 0.2 VCC VSS + 0.3 0.8 0.2 VCC -- -- 0.4 0.4
Unit Remarks
V V V V V V V V V V V V V V
*1 *2 *2 *1 *2 *2
"H" level output voltage
VOH
"L" level output voltage
VOL
Pull-up resistance
Rpu
--
30
--
100
k
ICC ICCS Supply current ICC ICCS ICCH Input pin capacitance Input leakage current Leakage current for open drain outputs Pull-down resistance CIN IIL Ileak Rpd Other than AVCC, AVSS, VCC,VSS VCC
VCC = +5.0 V10% 16 MHz internal operation VCC = +3.0 V10% 8 MHz internal operation VCC = +5.0 V10% TA = 25C --
-- -- -- -- -- -- -10 -- 40
50 25 10 5 0.1 10 -- 0.1 --
70 30 20 10 10 -- 10 10 200
mA mA mA mA A pF A A k
Other than P60 VCC = 5.5 V to P67 VSS < VI < VCC Other than P60 to P67 MD2 -- --
*1: Hysteresis input pins: RST, HST, P60 to P67, P70 to P76, P80 to P86, P90 to P95, PA1 to PA7 *2: TTL input pins: AD00/D00 to AD07/D07, AD08/D08/P10 to AD15/D15/P17, HRQ/P53, RDY/P51
49
MB90610A Series
4. AC Characteristics
(1) Clock Timing * When VCC = +5.0 V10%
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time Frequency variation ratio* (when locked) Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
Symbol fC tC f PWH PWL tcr tcf fCP tCP
Pin name X0, X1 X0, X1 -- X0 X0 -- --
Conditions -- -- -- -- -- -- --
Value Min. 3 31.25 -- 10 -- 1.5 62.5 Max. 32 333 3 -- 5 16 666
Unit MHz ns % ns ns MHz ns
Remarks
The duty ratio should be in the range 30 to 70%
* : The frequency variation ratio is the maximum variation from the specified central frequency when the multiplier PLL is locked. The value is expressed as a proportion.
f =
+
f0
x 100 (%)
Central frequency f0 -
* When VCC = +2.7 V (min.)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time 50
Symbol fC tC PWH PWL tcr tcf fCP tCP
Pin name X0, X1 X0, X1 X0 X0 -- --
Conditions -- -- -- -- -- --
Value Min. 3 62.5 20 -- 1.5 125 Max. 16 333 -- 5 8 666
Unit MHz ns ns ns MHz ns
Remarks
The duty ratio should be in the range 30 to 70%
MB90610A Series
* Clock Timing
tC 0.8 VCC 0.2 VCC PWH tcf PWL tcr
* PLL Operation Assurance Range
Relationship between the internal operating clock frequency and supply voltage Normal operation range Power supply VCC (V) 5.5
4.5
3.3 2.7 PLL operation assurance range fCP (MHz)
1.5
3
8
16
Internal clock Relationship between the oscillation frequency and internal operating clock frequency Multiply Multiply by 4 by 3
16
No multiplier Multiply by 1
Multiply by 2 Internal Clock fCP (MHz) 12
9 8
4
34
8
16 Oscillation clock fC (MHz)
24
32
Note: Low voltage operation down to 2.7V is also assured for the evaluation tools.
51
MB90610A Series
The AC characteristics are for the following measurement reference voltages. * Input Signal Waveform
Hysteresis input pins 0.8 VCC 0.2 VCC
* Output Signal Waveform
Output pins 2.4 V 0.8 V
Other than hysteresis/MD input pins 0.7 VCC 0.3 VCC
(2) Clock Output Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
Pin name CLK
Conditions VCC = +5 V10%
Value Min. tCP tCP/2 - 20 Max. -- tCP/2 + 20
Unit ns ns
Remarks
tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V
52
MB90610A Series
(3) Recommended Resonator Manufacturers * Sample Application of Piezoelectric Resonator (FAR Family)
X0
X1 R FAR
*1
C1
*2
C2
*2
*1: Fujitsu Acoustic Resonator
FAR part number Frequency Dumping (built-in capacitor type) (MHz) resistor FAR-C4CC-02000-L20 FAR-C4CA-04000-M01 FAR-C4CB-08000-M02 FAR-C4CB-10000-M02 FAR-C4CB-16000-M02 Inquiry: FUJITSU LIMITED 2.00 4.00 8.00 10.00 16.00 1 k -- -- -- --
Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5% 0.5% 0.5% 0.5%
Temperature Loading characteristics of FAR frequency capacitors*2 (TA = -20C to +60C) 0.5% 0.5% 0.5% 0.5% 0.5% Built-in
53
MB90610A Series
* Sample Application of Ceramic Resonator
X0
X1 R
*1 *4
C1
*2
C2
*3
Resonator manufacturer*1
Resonator KBR-2.0MS PBRC2.00A KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B KBR-10.0M PBRC10.00B KBR-12.0M PBRC12.00B
Frequency (MHz) 2.00
C1 (pF)*2 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in
C2 (pF)*3 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in
R*4 Not required Not required 680 680 680 680 Not required Not required Not required Not required 560 Not required Not required 330 680 330 680
4.00
Kyocera Corporation
6.00
8.00
10.00 12.00
(Continued)
54
MB90610A Series
(Continued)
Resonator manufacturer*1 Resonator CSA2.00MG040 CST2.00MG040 CSA4.00MG040 CST4.00MGW040 CSA6.00MG CST6.00MGW CSA8.00MTZ CST8.00MTW CSA10.00MTZ CST10.00MTW CSA12.00MTZ CST12.00MTW CSA16.00MXZ040 CST16.00MXW0C3 CSA20.00MXZ040 CSA24.00MXZ040 CSA32.00MXZ040 Frequency (MHz) 2.00 4.00 6.00 8.00 10.00 12.00 16.00 20.00 24.00 32.00 C1 (pF)*2 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 C2 (pF)*3 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 R*4 Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required Not required
Murata Mfg. Co., Ltd.
Inquiry: Kyocera Corporation * AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 * AVX Limited European Sales Headquarters: TEL 44-1252-770000 * AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
55
MB90610A Series
(4) Reset and Hardware Standby Inputs
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Reset input time
Symbol tRSTL
Pin name RST HST
Conditions --
Value Min. 16 tCP 16 tCP Max. -- --
Unit ns ns
Remarks
Hardware standby input time tHSTL
tRSTL, tHSTL
RST HST 0.2 VCC 0.2 VCC
* Conditions for Measurement of AC Reference
Pin
CL: Load capacity during testing For CLK and ALE, CL = 30 pF. For address and data buses (AD15 to AD00), RD and WR, CL = 80 pF.
CL
56
MB90610A Series
(5) Power-on Reset
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rise time Power supply cut-off time
Symbol tR tOFF
Pin name VCC VCC
Conditions
Value Min. -- Max. 30 --
Unit ms ms *
Remarks
--
1
For repetition of the operation
* : VCC should be lower than 0.2 V before power supply rise. Notes: * The above values are the values required for a power-on reset * When HST = "L", this standard must be followed to turn on power supply for power-on reset whether or not necessary. * The device has built-in registers which are initialized only by power-on reset. For possible initialization of these registers, turn on power supply according to this standard.
tR
VCC
2.7 V 0.2 V tOFF 0.2 V
Abrupt changes in the power supply voltage may cause a power-on reset. When changing the power supply voltage during operation, the change should be as smooth as possible, as shown in the following figure. Main power supply voltage
Sub power supply voltage VSS
The gradient should be no more than 50mV/ms.
57
MB90610A Series
(6) Bus Timing (Read)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter ALE pulse width
Symbol tLHLL
Pin name ALE Address Address RD, Address Address/ data
Conditions
Value Min. Max. -- -- -- -- -- -- 5 tCP/2 - 60 5 tCP/2 - 80 -- 3 tCP/2 - 60 3 tCP/2 - 80 -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
VCC = +5.0 V10% tCP/2 - 20 VCC = +3.0 V10% tCP/2 - 35 VCC = +5.0 V10% tCP/2 - 20 VCC = +3.0 V10% tCP/2 - 40 tCP/2 - 15 -- tCP - 15 -- -- 3 tCP/2 - 20
Valid address ALE time tAVLL ALE address valid time tLLAX Valid address RD time Valid address valid data input tAVRL
VCC = +5.0 V10% VCC = +3.0 V10% -- VCC = +5.0 V10%
tAVDV
RD pulse width
tRLRH
RD
RD valid data input RD data hold time RD ALE time RD address valid time
tRLDV
Data
-- VCC = +3.0 V10% 0
tRHDX tRHLH tRHAX RD, ALE Address, RD Address, CLK RD, CLK --
tCP/2 - 15 tCP/2 - 10 tCP/2 - 20 tCP/2 - 20
Valid address CLK time tAVCH RD CLK time tRLCH
58
MB90610A Series
tAVCH CLK 2.4 V
tRLCH 2.4 V
tAVLL ALE 2.4 V tLHLL tAVRL
tLLAX 2.4 V 0.8 V tRLRH
tRHLH 2.4 V
RD
2.4 V 0.8 V tRHAX 2.4 V 0.8 V tRLDV tAVDV 2.4 V 0.8 V Address 2.4 V 0.8 V 2.2 V 0.8 V Read data tRHDX 2.2 V 0.8 V tRHAX 2.4 V 0.8 V tAVDV tAVDV tRLDV tRHDX 2.2 V 0.8 V Read data 2.2 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V
Multiplex mode
A23 to A16
Non-multiplex mode
A23 to A00
D15 to D00
59
MB90610A Series
(7) Bus Timing (Write)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Valid address WR time WR pulse width Valid data output WR time WR data hold time WR address valid time WR ALE time WR CLK time
Symbol tAVWL tWLWH tDVWH
Pin name Address WRL, WRH
Conditions
Value Min. tCP - 15 3 tCP/2 - 20 3 tCP/2 - 20 Max. -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns
Remarks
--
Data tWHDX tWHAX tWHLH tWLCL Address ALE, WRL, WRH WRL, WRH, CLK
VCC = +5.0 V10% VCC = +3.0 V10%
20 30 tCP/2 - 10
--
tCP/2 - 15 tCP/2 - 20
tWLCH CLK 2.4 V
tWHLH ALE 2.4 V
tAVWL
tWLWH 2.4 V 0.8 V tWHAX
WR (WRL, WRH)
Multiplex mode
A23 to A16 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V Write data
2.4 V 0.8 V tWHDX 2.4 V 0.8 V tWHAX
Non-multiplex mode
A23 to A00 2.4 V 0.8 V tDVWH D15 to D00 2.4 V 0.8 V Write data
2.4 V 0.8 V tWHDX tWHDX 2.4 V 0.8 V
60
MB90610A Series
(8) Ready Input Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
Pin name RDY RDY
Conditions VCC = +5.0 V10% VCC = +3.0 V10% --
Value Min. 45 70 0 Max. -- -- --
Unit ns ns ns
Remarks
Note: Use the auto-ready function if the setup time at fall of the RDY is too short.
CLK ALE
2.4 V
2.4 V
RD/WR
tRYHS RDY (Wait cycle) 0.2 VCC
tRYHS 0.2 VCC
tRYHS RDY (No wait cycle) 0.8 VCC 0.8 VCC tRYHH
61
MB90610A Series
(9) Hold Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Pin floating HAK time HAK pin valid time
Symbol tXHAL tHAHV
Pin name HAK HAK
Conditions -- --
Value Min. 30 tCP Max. tCP 2 tCP
Unit ns ns
Remarks
Note: After reading HRQ, more than one cycle is required before changing HAK.
HRQ
HAK
2.4 V 0.8 V tXHAL tHAHV High impedance
Pin
62
MB90610A Series
(10) I/O Expansion Serial Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK
Symbol tSCYC tSLOV tIVSH
Pin name SCK0 to 2 SCK0 to 2 SOT0 to 2 SCK0 to 2 SIN0 to 2 SCK0 to 2 SIN0 to 2 SCK0 to 2 SCK0 to 2 SCK0 to 2 SOT0 to 2 SCK0 to 2 SIN0 to 2 SCK0 to 2 SIN0 to 2
Conditions -- VCC = +5.0 V10% VCC = +3.0 V10% VCC = +5.0 V10% VCC = +3.0 V10% VCC = +5.0 V10% VCC = +3.0 V10% -- -- VCC = +5.0 V10% VCC = +3.0 V10% VCC = +5.0 V10% VCC = +3.0 V10% VCC = +5.0 V10% VCC = +3.0 V10%
Value Min. 8 tCP -80 -120 100 200 60 120 4 tCP 4 tCP -- -- 60 120 60 120 Max. -- 80 120 -- -- -- -- -- -- 150 200 -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
SCK valid SIN hold tSHIX time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK tSHSL tSLSH tSLOV tIVSH
CL = 80 pF + 1 TTL for the internal shift clock mode output pin.
CL = 80 pF + 1 TTL for the external shift clock mode output pin.
SCK valid SIN hold tSHIX time
Notes: * These are the AC characteristics for CLK synchronous mode. * CL is the load capacitance connected to the pin at testing. * tCP is the machine cycle period (unit: ns).
63
MB90610A Series
* Internal Shift Clock Mode
tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 2.4 V 0.8 V
* External Shift Clock Mode
tSLSH SCK 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
tSHSL 0.8 VCC
tSHIX 0.8 VCC 0.2 VCC
64
MB90610A Series
(11) Timer Input Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Input pulse width
Symbol
Pin name
Conditions --
Value Min. 4 tCP Max. --
Unit ns
Remarks
tTIWH/L TIN0 to 1
* Timer Input Timing
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(12) Timer Output Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name TOT0 to 1
Conditions VCC = +5.0 V10% VCC = +3.0 V10%
Value Min. 30 80 Max. -- --
Unit ns ns
Remarks
CLK TOUT change timing tTO
* Timer Output Timing
CLK
2.4 V
TOUT
2.4 VCC 0.8 VCC tTO
65
MB90610A Series
(13) Trigger Input Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol tTRGH tTRGL
Pin name ATG INT0 to INT1
Conditions
Value Min. 5 tCP Max. --
Unit
Remarks
Input pulse width
--
ns
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
tTRGH
tTRGL
(14) Chip Select Output Timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Conditions VCC = +5.0 V10%
Value Min. -- -- tCP/2 - 10 tCP/2 - 10 -- Max. 5 tCP/2 - 60 5 tCP/2 - 80 -- -- tCP/2 - 20
Unit ns ns ns ns ns
Remarks
Chip select enabled Valid data input time RD Chip select enabled time WR Chip select enabled time Enabled chip select CLK time
tSVDV
CS0 to CS7 D15 to D00 VCC = +3.0 V10% CS0 to CS7 RD CS0 to CS7 WRH, WRL CS0 to CS7 CLK
tRHSV tWHSV tSVCH
-- -- --
66
MB90610A Series
tSVCH CLK 2.4 V
RD
2.4 V
tRHSV A23 to A00 CS0 to CS7 2.4 V 0.8 V tSVDV D15 to D00 2.4 V 0.8 V tWHSV WR (WRL, WRH) 2.4 V Read data
D15 to D00
Write data
67
MB90610A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Analog port input current Analog input voltage
Symbol Pin name -- -- -- -- VOT VFST -- IAIN VAIN -- -- -- -- -- AN0 to AN7 AN0 to AN7 -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH -- AN0 to AN7
Value Min. -- -- -- -- AVRL - 1.5 AVRH - 4.5 6.125*1 12.25*2 -- AVRL AVRL + 2.7 0 -- -- -- -- -- Typ. 10 -- -- -- AVRL + 0.5 AVRH - 1.5 -- -- 0.1 -- -- -- 3 -- 200 -- -- Max. 10 3.0 2.0 1.5 AVRL + 2.5 AVRH + 0.5 -- -- 10 AVRH AVCC AVRH - 2.7 -- 5*3 -- 5
*3
Unit bit LSB LSB LSB LSB LSB s s A V V V mA A A A LSB
Reference voltage -- Power supply current IA IAH IR IRH
Reference voltage supply current Variation between channels
4
*1: For VCC = +5.0 V10% and a 16 MHz machine clock *2: For VCC = +3.0 V10% and a 8 MHz machine clock *3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = +5.0 V). Notes: * The relative error increases as |AVRH - AVRL| decreases. * The output impedance of the external circuit for the analog input should be in the following range. Output impedance of external circuit < approx. 7 k * If the output impedance of the external circuit is too high, the sampling time for the analog voltage may be too short. (Sampling time = 3.75 s @4 MHz (This corresponds to 16 MHz internal operation if the multiplier is 4.)) * For an external capacitor to be provided outside the chip, its capacity should desirably be thousands times larger than that of the capacity in the chip taking in consideration the influence of the capacity distribution of the external and internal capacitors.
68
MB90610A Series
* Model of The Analog Input Circuit
Analog input RON1 RON2 RON3 Sample and hold circuit C0 Comparator RON4 C1
RON1 = 1.5 k (approx.) (VCC = 5.0 V) RON2 = 0.5 k (approx.) (VCC = 5.0 V) RON3 = 0.5 k (approx.) (VCC = 5.0 V) RON4 = 0.5 k (approx.) (VCC = 5.0 V) C0 = 60 pF (approx.) C1 = 4 pF (approx.) Note: The above values are for reference only.
6. A/D Converter Glossary
* Resolution The change in analog voltage that can be recognized by the A/D converter. If the resolution is 10 bits, the analog voltage can be resolved into 210 = 1024 steps. * Total error The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and noise. * Linearity error The deviation between the actual conversion characteristic of the device and the line linking the zero transition point (00 0000 0000 00 0000 0001) and the full scale transition point (11 1111 1110 11 1111 1111). * Differential linearity error The variation from the ideal input voltage required to change the output code by 1 LSB.
Digital output 11 1111 1111 11 1111 1110
* * * * * * * * * * *
(1 LSB x N + VOT)
Linearity error
00 0000 0010 00 0000 0001 00 0000 0000 VOT VFST - VOT 1022 VNT - (1 LSB x N + VOT) 1 LSB V(N + 1)T - VNT 1 LSB (LSB) - 1 (LSB) VNT V(N + 1)T
Analog input VFST
1 LSB =
Linearity error =
Differential linearity error =
69
MB90610A Series
s EXAMPLES CHARACTERISTICS
(1) "H" Level Output Voltage (2) "L" Level Output Voltage
VOH - IOH VOH (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -2 -4 -6
VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V
-8 IOH (mA)
VOL (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2 4
VOL - IOL
VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V
6
8 IOL (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage
(4) "H" Level Input Voltage/"L" Level Input Voltage
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
VIN - VCC (CMOS Input)
TA = +25C
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2
VIN - VCC (Hysteresis Input)
TA = +25C
VIHS VILS
3
4
5
6 VCC (V)
2
3
4
5
6 VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
70
MB90610A Series
(5) Power Supply Current (fcp = internal frequency)
ICC (mA) 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 ICC - VCC TA = +25C fcp = 16 MHz fcp = 12.5 MHz ICCS (mA) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 ICCS - VCC TA = +25C fcp = 16 MHz
fcp = 12.5 MHz
fcp = 8 MHz fcp = 4 MHz
fcp = 8 MHz fcp = 4 MHz
4.0
5.0
6.0 VCC (V)
4.0
5.0
6.0 VCC (V)
IA (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0
IA - AVCC TA = +25C fCP = 16 MHz
IR (mA) 0.30
IR - AVR TA = +25C fCP = 16 MHz
0.20
0.10
0 4.0 5.0 6.0 AVCC (V) 3.0 4.0 5.0 6.0 AVR (V)
(6) Pull-up Resistance
R - VCC R (k ) 1000 TA = +25C
100
10 2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0 VCC (V)
71
MB90610A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
72
MB90610A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b
(Continued)
73
MB90610A Series
(Continued)
Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
74
MB90610A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand (c) word (d) long
Number Number Number Number Number Number of of of of cycles access of cycles access of cycles access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4
Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits)
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
75
MB90610A Series
Table 7
Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ ~ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a)
Transfer Instructions (Byte) [41 Instructions]
RG 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) LH AH Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
76
MB90610A Series
Table 8
Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP A , RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16 # 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+
Transfer Instructions (Word/Long Word) [38 Instructions]
~ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 4 5+ (a) 3 4 5+ (a) RG 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2x (c) 0 2x (c) 0 (d) 0 0 (d) Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - N * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A, ear A, eam RWi, ear RWi, eam A, ear A, eam A, #imm32 ear, A eam, A
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
77
MB90610A Series
Table 9
Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
# 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 RG 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 B 0 (b) 0 (b) 0 2x b) 0 0 (b) 0 0 (b) 0 (b) 0 2x(b) 0 0 (b) 0 0 0 (c) 0 0 2x(c) 0 (c) 0 0 (c) 0 0 2x(c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (decimal) byte (A) (A) -imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 LH AH I S T N Z V C RMW Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
A, ear 2 A, eam 2+ A, #imm32 5 A, ear 2 A, eam 2+ A, #imm32 5
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
78
MB90610A Series
Table 10
Mnemonic INC INC DEC DEC INCW INCW DECW DECW INCL INCL DECL DECL ear eam ear eam ear eam ear eam ear eam ear eam
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
# 2 2+ 2 2+ 2 2+ 2 2+ 2 2+ 2 2+ ~ 2 5+ (a) 3 5+ (a) 3 5+ (a) 3 5+ (a) 7 9+ (a) 7 9+ (a) RG 2 0 2 0 2 0 2 0 4 0 4 0 B Operation LH AH - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - S - - - - - - - - - - - - T - - - - - - - - - - - - N * * * * * * * * * * * * Z * * * * * * * * * * * * V * * * * * * * * * * * * C - - - - - - - - - - - - RMW - * - * - * - * - * - * 0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11
Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # 1 2 2+ 2 1 2 2+ 3 2 2+ 5
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3 RG 0 1 0 0 0 1 0 0 2 0 0 B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32 LH AH - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - S - - - - - - - - - - - T - - - - - - - - - - - N * * * * * * * * * * * Z * * * * * * * * * * * V * * * * * * * * * * * C RMW * * * * * * * * * * * - - - - - - - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
79
MB90610A Series
Table 12
Mnemonic DIVU DIVU DIVU DIVUW DIVUW MULU MULU MULU A A, ear # 1 2
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
~ *1 *2 *3 *4 *5 RG 0 1 0 1 0 0 1 0 0 1 0 B 0 0 *6 0 *7 Operation word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) long (A)/word (ear) Quotient word (A) Remainder word (ear) long (A)/word (eam) Quotient word (A) Remainder word (eam) LH AH I S T N Z V C RMW - - - - - - - - - - - - - - - - - - - - - - ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - -
A, eam 2+ A, ear 2
A, eam 2+
A 1 *8 A, ear 2 *9 A, eam 2+ *10
0 byte (AH) *byte (AL) word (A) 0 byte (A) *byte (ear) word (A) (b) byte (A) *byte (eam) word (A) 0 word (AH) *word (AL) long (A) 0 word (A) *word (ear) long (A) (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13
*1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
80
MB90610A Series
Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]
Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A A, #imm16 A, ear A, eam ear, A eam, A A ear eam # 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ ~ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) RG 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
81
MB90610A Series
Table 14
Mnemonic ANDL ANDL ORL ORL XORL XORL A, ear A, eam A, ear A, eam A, ea A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a)
Logical 2 Instructions (Long Word) [6 Instructions]
RG 2 0 2 0 2 0 B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH - - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V R R R R R R C RMW - - - - - - - - - - - -
Table 15
Mnemonic NEG NEG NEG A ear eam # 1 2 2+ 1 2 2+ ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG 0 2 0 0 2 0 B 0 Operation byte (A) 0 - (A) LH AH X - - - - - - - - - - - I - - - - - - S - - - - - - T - - - - - - N * * * * * * Z * * * * * * V * * * * * * C * * * * * * RMW - - * - - *
3 5+ (a) 2 3 5+ (a)
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A) 0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
NEGW A NEGW ear NEGW eam
Table 16
Mnemonic NRML A, R0 # 2 ~ *1 RG 1
Normalize Instruction (Long Word) [1 Instruction]
B 0 Operation LH AH - I - ST - - N - Z V C RMW * - - - long (A) Shift until first digit is "1" - byte (R0) Current shift count
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
82
MB90610A Series
Table 17
Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0 # 2 2 ~ 2 2 RG 0 0 2 0 2 0 1 1 1 0 0 0 1 1 1 1 1 1
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
B 0 0 0 2x(b) 0 2x(b) 0 0 0 0 0 0 0 0 0 0 0 0 Operation byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0) LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - S T N Z V C RMW * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * - - - * - * - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
--* --* --- --* --* --- --* --* --- --* --* ---
ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 2 2 2
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
83
MB90610A Series
Table 18
Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+(a) 5 6+(a) 4 6 7+(a) 6 7 10 11+(a) 10 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2x(c) (c) 2x(c) 2x(c) *2 2x(c)
Branch 1 Instructions [31 Instructions]
Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15 (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15 (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - STN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - V C RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6
CALLP @eam *6 CALLP addr24 *7
-- --
*1: *2: *3: *4: *5: *6: *7:
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
84
MB90610A Series
Table 19
Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE ear, #imm8, rel CBNE eam, #imm8, rel*9 CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*9 DBNZ DBNZ ear, rel eam, rel # 3 4 4 4+ 5 5+ 3 ~ RG *1 *1 *2 *3 *4 *3 *5 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0
Branch 2 Instructions [19 Instructions]
B 0 0 0 (b) 0 (c) 0 Operation Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16 LH AH I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - R R R R * - STNZ - - - - - - - - - - S S S S * - - - - - - - - - - - - - - - * - * * * * * * * * * * - - - - * - * * * * * * * * * * - - - - * - V C RMW * * * * * * * * * * - - - - * - * * * * * * - - - - - - - - * - - - - - - - - * - * - - - - - -
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2x(b) Branch when byte (eam) = (eam) - 1, and (eam) 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x(c) Branch when word (eam) = (eam) - 1, and (eam) 0 0 8x(c) 6x(c) 6x(c) 8x(c) 6x(c) (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#local8
UNLINK RET *7 RETP *8
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
*1: *2: *3: *4: *5: *6: *7: *8: *9:
5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
85
MB90610A Series
Table 20
Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX AND OR A AH PS rlst @A CCR, #imm8 CCR, #imm8 # 1 1 1 2 1 1 1 2 1 2 2 2 2
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 RG 0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 B (c) (c) (c) *4 (c) (c) (c) *4 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n LH AH I - - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - S T N Z V C RMW - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--- --- *** --- * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) (CCR) and imm8 byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank
MOV RP #imm8 , MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A
--- --- - - - - - - - - - - - -
2 3 2+ 2+ (a) 2 1 2+ 1+ (a) 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
--- --- --- --- - - - - - - - - - - - - - - - - - - - - -
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count (c), or push count (c) *1: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
86
MB90610A Series
Table 21
Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB SETB SETB dir:bp addr16:bp io:bp # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Manipulation Instructions [21 Instructions]
B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b LH AH I Z Z Z - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - S T N Z V C RMW * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - -
--- --- --- --- --- ---
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- ---- * * * * * * * - - - - - - -
CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp
2x (b) Branch when (addr16:bp) b = 1, bit = 1 - *5 *5 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 - -
------ ------
*1: *2: *3: *4: *5:
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
87
MB90610A Series
Table 22
Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
# 1 1 1 1 1 1 ~ 3 2 1 2 1 1 RG B 0 0 0 0 0 0 0 0 0 0 0 0 Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH - - X - Z - - * - X - Z I - - - - - - ST - - - - - - - - - - - - N - - * * R R Z - - * * * * V C RMW - - - - - - - - - - - - - - - - - -
Table 23
Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI # 2 2 2 2 2 2 2 2 2 2 ~ *2 *2 *1 *1 6m+6 *2 *2 *1 *1 6m+6 RG B *5 *5 *5 *5 *5 *8 *8 *8 *8 *8
String Instructions [10 Instructions]
Operation LH AH - - - - - - - - - - - - - - - ISTN --- --- --- --- --- --- --- --- --- --- - - * * * - - * * * Z V C RMW - - * * * - - * * * - - * * - - - * * - - - * * - - - * * - - - - - - - - - - -
*3 Byte transfer @AH+ @AL+, counter = RW0 *3 Byte transfer @AH- @AL-, counter = RW0 *4 Byte retrieval (@AH+) - AL, counter = RW0 *4 Byte retrieval (@AH-) - AL, counter = RW0 *3 Byte filling @AH+ AL, counter = RW0
*6 Word transfer @AH+ @AL+, counter = RW0 - *6 Word transfer @AH- @AL-, counter = RW0 - *7 Word retrieval (@AH+) - AL, counter = RW0 *7 Word retrieval (@AH-) - AL, counter = RW0 *6 Word filling @AH+ AL, counter = RW0 - - -
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
88
MB90610A Series
s ORDERING INFORMATION
Part number MB90611APFV MB90611APF Package 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) Remarks
89
MB90610A Series
s PACKAGE DIMENSIONS
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 +.008 .059 -.004
+0.20
(Mounting height)
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016)
80 81
3.35(.132)MAX
51 50
20.000.20(.787.008)
0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10 0.800.20 (.031.008) Details of "B" part
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
90
MB90610A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9907 (c) FUJITSU LIMITED Printed in Japan
91

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